000			00439nam a2200169Ia 4500
999			_c34407 _d34407
005			20180329142934.0
008			180223s9999||||xx |||||||||||||| ||und||
020			_a9781138099951
040			_aUPES LIBRARY _bEnglish
082			_a621.381 _bCAV
100			_aCavanagh, Joseph _952456
245		0	_aVerilog HDL design examples
260			_aBoca Raton: _bCRC, _c2018
300			_axv, 655p.
650			_aElectronics _962494
942			_cREF